Modelling and analyzing multi-core COTS processors - Certifiability of multi and many-cores architectures Access content directly
Conference Papers Year : 2022

Modelling and analyzing multi-core COTS processors

Abstract

To embed multi-core COTS processors in an avionic product, the platform must be thoroughly analyzed from two perspectives: the worst case real-time behaviours and the safety impact of internal failures. Both activities are very complex and error-prone for large size systems. Moreover, the frameworks for both perspectives (real-time and safety) are completely decoupled, leading to independent and possibly incoherent analyses. Our purpose is to unify both worlds and help designers in their certification process. To this end, we have formalized and unified as much as possible the different perspectives of multi-core analysis. We have also proposed a simple description language for the platform, which contains the minimal concepts needed by both perspectives, as well as an automatic translation to the two analysis frameworks.
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Dates and versions

hal-03761937 , version 1 (26-08-2022)

Identifiers

  • HAL Id : hal-03761937 , version 1

Cite

Frédéric Boniol, Julien Brunel, Kevin Delmas, Claire Pagetti, Victor Jegu. Modelling and analyzing multi-core COTS processors. 11th European Congress on Embedded Real Time Software and Systems (ERTS 2022), Jun 2022, Toulouse, France. ⟨hal-03761937⟩
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